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AR2SEC completes final milestone: a validated RISC-V platform for safety-critical applications

The AR2SEC project has reached its final milestone, closing a two-year R&D journey that has produced a functional, validated computing platform based on RISC-V architecture — designed from the ground up for deployment in safety-critical environments.

AR2SEC completes final milestone: a validated RISC-V platform for safety-critical applications

On April 15 and 16, the AR2SEC consortium held its final project review with the CDTI, completing the justification process for all activities carried out in 2025. The two-day session combined a remote presentation of technical activities with an in-person demonstration of the physical hardware, giving auditors a hands-on view of the platform's capabilities.

A platform built for critical systems

AR2SEC set out to develop a computing platform based on the open RISC-V architecture, targeting applications where reliability and functional safety are non-negotiable. Over the course of the project, the consortium integrated communication IP Cores, a Coarse-Grained Reconfigurable Array (CGRA) accelerator, and dedicated functional safety modules into a single, coherent hardware and software ecosystem.

In Milestone 3, all components were successfully brought together into a working, integrated platform. Milestone 4 took validation a step further: the architecture was tested through three vertical demonstrators in automotive, avionics, and robotics, proving its performance across very different application profiles.

GTD's contribution to the robotics demonstrator validated the correct behaviour of the platform in a real embedded control scenario. For readers interested in the technical details, our earlier article covers the RISC-V platform architecture in depth: Plataforma RISC-V para sistemas críticos.

Towards an ASIC

Beyond validation, the project also delivered a technical study on adapting the platform for other sectors, and a feasibility analysis for future production of the design as an ASIC, a custom chip that would bring the platform's capabilities to industrial-scale deployment.

A consortium effort

AR2SEC brought together complementary expertise across five organisations: CLUE, TEB, FENTISS, the Barcelona Supercomputing Center (BSC), and the Universidad Politécnica de Madrid (UPM). The project was supervised by Carlos del Val Merino at CDTI.

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